efabless corporation is an open innovation, hardware creation platform for “smart” products. Our community delivers the customized integrated electronics required for semiconductor and hardware system innovators to turn their product visions into a marketable reality.
Today, efabless focuses on on-demand and custom IP. Efabless gives chip companies two ways to obtain analog & mixed-signal IP: you can search for existing IP in our growing library of verified designs, but more importantly you can also request the efabless community to design new IP and derivatives.
We are opening new markets. Our initial application for the service is to fill the need by foundries, design service firms and IC providers for on-demand and custom IP. For example, foundries post design requests or search our marketplace to fill gaps in IP for process nodes. Design firms and IC companies, large and small, access efabless and its community to source custom analog and digital IP for new designs. We will soon provide full chip assembly and our community will serve hardware innovators requiring customized electronics solutions.
efabless focuses on Ad (Big A-little d) IP at this time. “Big A” means primarily analog circuits. “Little d” means digital circuits as necessary to build powerful mixed signal IP and ICs. .
Community members retain the rights to IP created on the system under the Technology Licensing Agreement. However, the IP is maintained on our system and is not available for downloading from the system. This is necessary to enable the ability to design with foundry PDK’s without requiring NDA’s.
This is one of the most unique and valuable aspects of the efabless system. We segment and protect your IP so that each individual involved with your design sees only those specifications and design files necessary to complete his job. The rest of the design is a “black box” represented by simulation models and vectors.
All IP files are abstracted and hidden from everyone except for the designer. If the IP is offered in the efabless marketplace, customers can only access the datasheets and abstracted views for simulation and integration - no schematics or gds data is exposed.
At efabless, the customer can search and purchase or license IP modules and more importantly the customer can also request derivatives and new IP directly in the efabless marketplace, including IP to be designed by the efabless community. Our “try before buying” solution allows a customer to integrate IP in a design and simulate it before user & licensing. This ensures first-time success and dramatically reduces the upfront cost and risk of design.
efabless developed a complete set of design software including system design, schematic entry, spice simulation, layout editing, DRC, LVS and parasitic extraction. Also a complete RTL-to-GDS digital design flow that includes synthesis, STA, placement and routing. We also offer a unique, community-oriented verification tool called Automatic Characterization Engine, or ACE. ACE is simulator agnostic and provides automatic verification of a design with reference to control specifications. All new designs must pass ACE certification before entering our efabless marketplace and customers and community can use the ACE tool to ensure a trusted conclusion to a design engagement.
At efabless we provide a full path from open IP to silicon products. Lowering the barrier for designer community to reach prototypes that can enable effective showcasing of the design work to the customers. The platform has three main pillars:
- A github-like openness for the design IP – as a “IP/IC Design Hub” with specific focus on Analog/Mixed-signal IP
- A complete foundry-supported design toolset to enable designers to adapt, implement and prototype their work based on the customer requirements.
- A customer focused marketplace for community-developed finished hard IP that originated from the design-hub.
First point, the shuttles: efabless offers community members and customers access to shuttles. Shuttles can be accessed on demand for premium pricing or on a Leave-When-Full basis that is very affordable. In the latter case, the shuttle cost per mm2 is within the low to high $100’s depending on the process technology. Keep in mind we focus on technologies like 180/130nm BCD and more mature 250/350nm with higher voltage support.
Second, characterization & testing: We designed an open source HW platform board, including a reference ASIC designed to enable characterization of community IP. The design has been silicon-proven on our platform and will be announced to the world in early 2017. The designers will then be able to fork the reference ASIC and replace the template design with their own IP. After fabrication, the designer will utilize the platform board and wakeup SW to validate their specific design. In the future, we intend to forge partnerships with companies offering labs and test facilities that support low volume production in different geographical regions. Through such partnerships, the efabless design community will access the capabilities as a part of an efabless ecosystem. Stay tuned as we publish our progress on this front.