PicoRV32 is a CPU core that implements the RISC-V RV32IMC Instruction Set. It can be configured as RV32E, RV32I, RV32IC, RV32IM, or RV32IMC core, and optionally contains a built-in interrupt controller. Tools (gcc, binutils, etc..) can be obtained via the RISC-V Website. The examples bundled with PicoRV32 expect various RV32 toolchains to be installed in /opt/riscv32i[m][c]. See the build instructions below for details. PicoRV32 is free and open hardware licensed under the ISC license (a license that is similar in terms to the MIT license or the 2-clause BSD license).
| Name | Description | Type | Direction | Vmin | Vmax |
|---|---|---|---|---|---|
| clk | clock input | signal | input | -0.5 | VDD + 0.3 |
| resetn | master reset (sense inverted) | signal | input | -0.5 | VDD + 0.3 |
| trap | error trap flag | signal | output | -0.5 | VDD + 0.3 |
| mem_valid | memory valid | signal | output | -0.5 | VDD + 0.3 |
| mem_instr | memory instruction | signal | output | -0.5 | VDD + 0.3 |
| mem_ready | memory ready | signal | input | -0.5 | VDD + 0.3 |
| mem_addr<31:0> | Memory address bus (32 bits) | digital | output | -0.5 | VDD + 0.3 |
| mem_wdata<31:0> | Memory write data (32 bits) | digital | output | -0.5 | VDD + 0.3 |
| mem_wstrb<3:0> | Memory write strobe (4 bits) | digital | output | -0.5 | VDD + 0.3 |
| mem_rdata<31:0> | Memory read data (32 bits) | digital | input | -0.5 | VDD + 0.3 |
| vdd! | Positive digital power supply | power | inout | 3.0 | 3.6 |
| gnd! | Digital Ground | ground | inout | 0 | 0 |
| Name | Typical | Minimum | Maximum | Units |
|---|---|---|---|---|
| VDD | 3.3 | V | ||
| Ground | 0 | V |
| Parameter | Typical | Minimum | Maximum | Units |
|---|---|---|---|---|
| device_area | 4274181.5 | µm² | ||
| area | 4274181.5 | µm² | ||
| width | 2099.2 | µm | ||
| height | 2036.1 | µm | ||
| DRC_errors | 0 | |||
| LVS_errors | 0 |
PICORV32
N/A
Clifford Wolf
Soft IP
350nm
Community
X-FAB
EFXH035C
Processor
Contact Designer
layout
8
1
Jun 23, 2017
