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Hydra version 2.0 SPI controller digital block.

  • Standard SPI slave controller
  • Dedicated register set for Hydra v2p0

Pins

Name Description Type Direction Vmin Vmax
SCK SPI clock input signal input -0.5 VDD + 0.3
RST SPI master reset signal input -0.5 VDD + 0.3
CSB SPI chip select (sense inverted) signal input -0.5 VDD + 0.3
SDI SPI data input signal input -0.5 VDD + 0.3
SDO SPI data output (tristate) signal output -0.5 VDD + 0.3
sdoena SPI data output enable (sense negative) signal output -0.5 VDD + 0.3
adcvalue<9:0> Input from ADC (10 bits) digital input -0.5 VDD + 0.3
adcdone Completion signal from ADC signal input -0.5 VDD + 0.3
bgap1ena Enable to bgap1 signal output -0.5 VDD + 0.3
bgap1trim<3:0> Trim to bgap1 digital output -0.5 VDD + 0.3
bgap2ena Enable to bgap2 signal output -0.5 VDD + 0.3
bgap2trim<3:0> Trim to bgap2 digital output -0.5 VDD + 0.3
bgap3ena Enable to bgap3 signal output -0.5 VDD + 0.3
bgap3trim<3:0> Trim to bgap3 digital output -0.5 VDD + 0.3
bgap4ena Enable to bgap4 signal output -0.5 VDD + 0.3
bgap4trim<3:0> Trim to bgap4 digital output -0.5 VDD + 0.3
bgena Enable to X-Fab bandgap IP signal output -0.5 VDD + 0.3
xtalena Enable to X-Fab xtal oscillator IP signal output -0.5 VDD + 0.3
adcena (unused) signal output -0.5 VDD + 0.3
adcrstb Enable to X-Fab ADC IP signal output -0.5 VDD + 0.3
adcconvert Conversion start to X-Fab ADC IP signal output -0.5 VDD + 0.3
VDD Positive digital power supply power inout 3.0 3.6
GND Digital Ground ground inout 0 0

Global Conditions

Name Typical Minimum Maximum Units
VDD 3.3 V
Ground 0 V

Physical Parameters

Parameter Typical Minimum Maximum Units
device_area µm²
area µm²
width µm
height µm
DRC_errors
LVS_errors

Figure(s)

hydra_spi_controller_symbol.svg

Figure 1

Performance Characteristics

Summary

Catalog ID

HYDRA_SPI_CONTROLLER

IP Provider

community

Designer

eFabless engineering

Type

Hard IP

Node

350nm

Vendor

efabless

Foundry

X-FAB

Process

EFXH035B

Category

N/A

Certifications

icon

Licensing

Info

Contact Designer

Maturity

Stage

layout

# of Tries

4

Library Package

Version

2.0

Version Date

Apr 27, 2018