The USB 2.0 dual role PHY is a Hi-Speed USB peripheral transceiver IP that implements the Intel® UTMI standard. It provides a High/Full-Speed USB analog front-end with a build-in 8-bit/16-bit parallel interface, therefore, it is easy to interface with USB2.0 device system.
It can work either as a host PHY or as a device PHY, depending on the different setting from controller.
Compliant with the USB Spec Rev2.0
Compliant with the UTMI Spec Rev1.05
Compliant with the UTMI+ Spec Rev1.0 Level3
Supports 480Mbit/s “High Speed”, 12Mbit/s “Full Speed” and 1.5Mbit/s “Low Speed”
Supports 60MHz/8-bit interface and 30MHz/16-bit interface
12MHz/24MHz external crystal, internal oscillator and PLL are used for generating high-speed internal clock and CLKOUT output
Internal terminations include 1.5Kohm pull-up resistor switching on DP/DM in the FS mode and the HS chirp mode
Clock and data recovery from serial stream on the USB bus
Supports detection of USB reset, suspend, resume and remote-wake-up features
Supports the test modes defined in the USB2.0 Specification
NRZI and Bit Stuff encoding and decoding
Supports low/full speed serial mode
Works as host PHY or device PHY by setting DPPULLDOWN and DMPULLDOWN
Process: GLOBALFOUNDRIES 0.13um 1.2v/3.3v 1P6/7/8M logic process
Supply voltage: 1.08v~1.2v~1.32v, 2.97v~3.3v~3.63v
Current consumption: < 50mA
Operating junction temperature: - 40°C ~ +25°C ~ +125°C
GDS size: 839*800 um2 with IO; 839*692 um2 without IO
GF13V33_USB20PHY_05
Vendor
VeriSilicon Microelectronics
Soft IP
130nm
VeriSilicon Microelectronics
GlobalFoundries
GF013
USB
Contact Designer
product
1
1.0
Oct 31, 2013
