This IP is a programmable Analog PLL suitable for high speed clock generation. The high speed VCO of this PLL can run up to 1000MHz. It contains a 1-64 input clock divider, a 1-128 feedback clock divider and a 1-8 output clock divider. By setting PLL_DM, PLL_DN and PLL_DP to different values, the output clock will be locked at different multiples of the input frequency.
GF13V33_PLL_07
Vendor
VeriSilicon Microelectronics
Soft IP
130nm
VeriSilicon Microelectronics
GlobalFoundries
GF013
Oscillator and Clocking
Contact Designer
product
1
1.0
May 27, 2014