A 32-bit timer with a prescaler.
It has input timer compare register (TMCMP), and timer overflow signal (TMROV) that is set when the counter exceeds the value in timer compare register. The timer overflow signal can be cleared by a control signal (TMROVCLR).
APB2TMR
Vendor
Efabless
Soft IP
N/A
Efabless
N/A
Timer
Contact Designer
silicon
2
1.0
Mar 14, 2020
