The JTAG TAP controller is used for development purposes (Boundary Scan testing, Memory BIST and debugging). It functions as an interface between the processor(s), peripheral cores, and any commercial debugger/emulator or Boundary Scan (BS) testing device. The external debugger or BS tester connects to the core via an IEEE 1149.1 compatible JTAG port. 

The TAP controller provides a connection to the external debugger and/or Boundary Scan testing equipment through the standard JTAG interface (IEEE Std. 1149.1 compliant). The external interface consists of five signals (TCK, TMS, TDI, TDO and TRST). The TAP controller is a 16-state finite state machine. The TAP moves from one state to another on the rising edge of TCK. The next state depends only on the TMS input. State outputs of the module (e.g. shift_dr_o) are active when the TAP controller is in the corresponding state. 

The TAP controller is just one part of the complete debugging system.