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apllc03_1v8
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Apllc03_1v8 is a 40-100MHz Phase-Lock-Loop clock multiplier circuit with built-in LPF. The cell generates a low jitter, CMOS level output clock whose frequency is 8 times higher than input reference clock.

  • PLL mode, VCO mode and standby mode
  • No need for external Low-Pass-Filter
  • Physical size (h x w): 155.24 μm x 270.78 μm (macro cell)
  • XH018, MOSLP, MET3, METMID, MIM module

Summary

Catalog ID

APLLC03_1V8

IP Provider

Foundry

Designer

X-FAB Engineer

Type

Hard IP

Node

180nm

Vendor

X-FAB

Foundry

X-FAB

Process

XH018

Category

Oscillator and Clocking

Certifications

icon

Licensing

Info

Contact Designer

Maturity

Stage

product

# of Tries

0

Library Package

Version

1.0

Version Date

Oct 05, 2017