X-Fab 12-bit address x 32 bit data single-port SRAM
| Name | Description | Type | Direction | Vmin | Vmax |
|---|---|---|---|---|---|
| CLK | clock input | signal | input | -0.5 | VDD18M + 0.3 |
| RDY | test output | signal | output | -0.5 | VDD18M + 0.3 |
| CEn | memory enable (sense inverted) | signal | output | -0.5 | VDD18M + 0.3 |
| WEn[31:0] | write enable (32 bits, sense inverted) | signal | output | -0.5 | VDD18M + 0.3 |
| OEn | output enable (sense inverted) | signal | input | -0.5 | VDD18M + 0.3 |
| A[11:0] | Memory address bus (12 bits) | digital | output | -0.5 | VDD18M + 0.3 |
| Q[31:0] | Memory data output (32 bits) | digital | output | -0.5 | VDD18M + 0.3 |
| D[31:0] | Memory data input (32 bits) | digital | input | -0.5 | VDD18M + 0.3 |
| VDD18M | Digital power supply | power | inout | 3.0 | 3.6 |
| VSSM | Digital Ground | ground | inout | 0 | 0 |
| Name | Typical | Minimum | Maximum | Units |
|---|---|---|---|---|
| VDD18M | 1.8 | V | ||
| Ground | 0 | V |
| Parameter | Typical | Minimum | Maximum | Units |
|---|---|---|---|---|
| device_area | µm² | |||
| area | µm² | |||
| width | µm | |||
| height | µm | |||
| DRC_errors | ||||
| LVS_errors | 0 |
Figure 1
XSPRAMBLP_4096X32_M32P
foundry
eFabless engineering
N/A
180nm
X-Fab
N/A
EFXH018D
N/A
Contact Designer
schematic
0
1.0
Jul 10, 2019