• Two power supply domains

– 1.8 V and 3.3 V power supply for read, write, store and recall

• I/O Configuration

– Separate input and output data buses

– Signal driven read access from EEPROM

– Signal driven write access to EEPROM

– Signal driven store access to EEPROM

– Signal driven recall access from EEPROM

• Options

– On-chip charge pump

– 2 separate controllable non-volatile memory parts (page 1 and page 2)

– External clock of 4 MHz 10% (outside of specified IP) is required for controlling non-volatile access.

• Serial Port

– DWSP (Diagnostic Wrapper Serial Port)

– Supports reduced IEEE P1500 standard (e.g. No bypass functionality).

– Allows access to NVRAM only or to all NVRAM connected to the same serial chain.

• Endurance / Data Retention

– Minimum 100000 store cycles to EEPROM 25 °C

– Minimum 10000 store cycles to EEPROM 125 °C

– Minimum 10000 store cycles to EEPROM 150 °C

– Minimum 1000 store cycles to EEPROM 175 °C

– Minimum 20 years data retention 125 °C (w/wo cycles)

– Minimum 6 years data retention 150 °C (w/wo cycles)

– Minimum 2 years data retention 175 °C (w/wo cycles)

• Power Consumption

– Zero static DC power consumption (intrinsic leakage only)