X-Fab 12-bit address x 8 bit data dual-port SRAM
Name | Description | Type | Direction | Vmin | Vmax |
---|---|---|---|---|---|
CLKA | port A clock input | signal | input | -0.5 | VDD18M + 0.3 |
CLKB | port B clock input | signal | input | -0.5 | VDD18M + 0.3 |
CEnA | port A memory enable (sense inverted) | digital | input | -0.5 | VDD18M + 0.3 |
CEnB | port B memory enable (sense inverted) | digital | input | -0.5 | VDD18M + 0.3 |
WEnA | port A write enable (sense inverted) | digital | input | -0.5 | VDD18M + 0.3 |
WEnB | port B write enable (sense inverted) | digital | input | -0.5 | VDD18M + 0.3 |
OEnA | port A output enable (sense inverted) | digital | input | -0.5 | VDD18M + 0.3 |
OEnB | port B output enable (sense inverted) | digital | input | -0.5 | VDD18M + 0.3 |
AA[11:0] | port A Memory address bus (12 bits) | digital | input | -0.5 | VDD18M + 0.3 |
AB[11:0] | port B Memory address bus (12 bits) | digital | input | -0.5 | VDD18M + 0.3 |
QA[7:0] | port A Memory data output (8 bits) | digital | output | -0.5 | VDD18M + 0.3 |
QB[7:0] | port B Memory data output (8 bits) | digital | output | -0.5 | VDD18M + 0.3 |
DA[7:0] | port A Memory data input (8 bits) | digital | input | -0.5 | VDD18M + 0.3 |
DB[7:0] | port B Memory data input (8 bits) | digital | input | -0.5 | VDD18M + 0.3 |
VDD18M | Digital power supply | power | inout | 3.0 | 3.6 |
VSSM | Digital Ground | ground | inout | 0 | 0 |
Name | Typical | Minimum | Maximum | Units |
---|---|---|---|---|
VDD18M | 1.8 | V | ||
Ground | 0 | V |
Parameter | Typical | Minimum | Maximum | Units |
---|---|---|---|---|
device_area | µm² | |||
area | µm² | |||
width | µm | |||
height | µm | |||
DRC_errors | ||||
LVS_errors |
Figure 1
XDPRAM_4096X8_M16P
foundry
eFabless engineering
N/A
180nm
X-Fab
N/A
EFXH018D
N/A
Contact Designer
schematic
1
1.0
Apr 16, 2019