Design Catalog Detail | Efabless

XDPRAM_4096X8_M16P

X-Fab

X-Fab 12-bit address x 8 bit data dual-port SRAM

full dual-port access
4096 x 8 bit memory

Pins

Name	Description	Type	Direction	V_min	V_max
CLKA	port A clock input	signal	input	-0.5	VDD18M + 0.3
CLKB	port B clock input	signal	input	-0.5	VDD18M + 0.3
CEnA	port A memory enable (sense inverted)	digital	input	-0.5	VDD18M + 0.3
CEnB	port B memory enable (sense inverted)	digital	input	-0.5	VDD18M + 0.3
WEnA	port A write enable (sense inverted)	digital	input	-0.5	VDD18M + 0.3
WEnB	port B write enable (sense inverted)	digital	input	-0.5	VDD18M + 0.3
OEnA	port A output enable (sense inverted)	digital	input	-0.5	VDD18M + 0.3
OEnB	port B output enable (sense inverted)	digital	input	-0.5	VDD18M + 0.3
AA[11:0]	port A Memory address bus (12 bits)	digital	input	-0.5	VDD18M + 0.3
AB[11:0]	port B Memory address bus (12 bits)	digital	input	-0.5	VDD18M + 0.3
QA[7:0]	port A Memory data output (8 bits)	digital	output	-0.5	VDD18M + 0.3
QB[7:0]	port B Memory data output (8 bits)	digital	output	-0.5	VDD18M + 0.3
DA[7:0]	port A Memory data input (8 bits)	digital	input	-0.5	VDD18M + 0.3
DB[7:0]	port B Memory data input (8 bits)	digital	input	-0.5	VDD18M + 0.3
VDD18M	Digital power supply	power	inout	3.0	3.6
VSSM	Digital Ground	ground	inout	0	0

Global Conditions

Name	Typical	Minimum	Maximum	Units
VDD18M	1.8			V
Ground	0			V

Physical Parameters

Parameter	Typical	Minimum	Maximum	Units
device_area				µm²
area				µm²
width				µm
height				µm
DRC_errors
LVS_errors

Figure(s)

Figure 1

Performance Characteristics

Summary

Catalog ID

XDPRAM_4096X8_M16P

IP Provider

foundry

Designer

eFabless engineering

Type

N/A

Node

180nm

Vendor

X-Fab

Foundry

N/A

Process

EFXH018D

Category

N/A

Certifications

Licensing

Info

Contact Designer

Maturity

Stage

schematic

# of Tries

1

Library Package

Version

1.0

Version Date

Apr 16, 2019