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Library Package

Dec 16, 2019


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Raptor is a full SoC reference design for IoT applications based on the Arm Cortex M0 or M3 CPU core targeted on the X-FAB XH018 process (180nm).  Raptor provides means to interface with analog and digital sensors as well as external RF radio (WIFI, Cellular, Bluetooth, etc.,) modules needed for IoT applications.

The reference design is based on an SoC design template and can be modified, compiled and simulated through the SoC Editor tool with CloudV on the Efabless platform. The reference design comes with basic device drivers for all on-chip peripherals as well as set of applications to test and demonstrate Raptor capabilities.

Instances of the Raptor Design Template can be configured through the Design Request Form.   A configuration file is generated upon saving the form and can be used as a starting point for generating a reference design or to request a turn-key delivery of a custom SoC through design partners on the Efabless platform.

Below is the block diagram for a Demo Chip configuration taped-out for Raptor.  The design files for project include an instance of Raptor based on the configuration shown below.


Block Diagram for Demo Chip Configuration


Raptor can be clocked using external or internal clock sources. Raptor has 10MHz internal RC oscillator as well as the necessary circuitry to attach external crystal oscillator (1-4 MHz). In addition to that, Raptor employs a PLL and clock dividers to enable the system to run at clock frequency that ranges from 500KHz up to 80 MHz under software control. The following diagram shows Raptor clocking subsystem.


Clock Tree


Demo Chip Layout


SoC Design Template

  • Cortex M0 CPU Core
  • AHB-Lite and APB buses
  • Up to 32 APB peripherals
  • Up to 8 AHB peripherals
  • Analog peripheral options include: ADC, DAC, Comparator
  • Digital peripheral options include: SPI, GPIO, I2C, UART, PWM/Timer
  • 8, 16 or 32kB internal SRAM memory
  • QSPI XIP memory controller for booting and executing from external serial Flash memory
  • Software configurable internal and external clock sources
  • Pre-designed clocking subsystem including PLL and clock dividers
  • Single power supply (3.3V)
  • On-board 1.8V LDO regulator
  • 3.3V I/O
  • JTAG port for testing only


Demo Chip Configuration

  • Cortex M0 hardened core
  • 16kB SRAM
  • AHB
    • 1 x 8-bit GPIO port
    • 1 x SPI master controller
  • APB
    • 1 x I2C master controller
    • 1 x SPI master controller
    • 2 x UART
    • 2 x PWM/Timer
    • 2 x 10-bit 8-channel ADC (4 inputs shared)
    • 1 x 10-bit DAC
    • 1 x Analog Comparator
  • JTAG port for testing
  • 56-pin QFN package (8x8 mm)


Pinout for Demo Chip