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Full-chip implementation of the PicoRV32 PicoSoC in X-FAB XH018. The raven chip contains two ADCs, a DAC, comparator, bandgap, RC oscillator, and over-temperature alarm, as well as 16 bits of general-purpose digital inputs/outputs. It is powered off of a single 3.3V supply and driven by a 5 to 12 MHz crystal. The core CPU clock speed is 8 times the crystal frequency.

  • 100 MHz clock rate
  • Selectable clock source
  • 16 channels GPIO
  • 2 ADCs
  • 1 DAC
  • 1 Comparator
  • Over-temperature alarm
  • 100 kHz RC oscillator
  • Selectable functions on GPIO outputs
  • Selectable interrupts on GPIO inputs

Pins

Name Description Type Direction Vmin Vmax
XCLK external 1-pin clock input signal input -0.5 VDD3V3 + 0.3
XI crytal oscillator input signal inout -0.5 VDD3V3 + 0.3
XO crytal oscillator output signal inout -0.5 VDD3V3 + 0.3
SDI standalone SPI data input signal input -0.5 VDD3V3 + 0.3
SCK standalone SPI clock signal input -0.5 VDD3V3 + 0.3
CSB standalone SPI chip select (sense inverted) signal input -0.5 VDD3V3 + 0.3
ser_rx UART receive channel signal input -0.5 VDD3V3 + 0.3
ser_tx UART transmit channel signal output -0.5 VDD3V3 + 0.3
irq Dedicated external interrupt signal input -0.5 VDD3V3 + 0.3
flash_csb Flash SPI chip select (active low) signal input -0.5 VDD3V3 + 0.3
flash_clk Flash SPI clock signal input -0.5 VDD3V3 + 0.3
flash_io0 Flash SPI channel 0 signal inout -0.5 xAVDD_N + 0.3
flash_io1 Flash SPI channel 0 signal inout -0.5 xAVDD_N + 0.3
flash_io2 Flash SPI channel 0 signal inout -0.5 xAVDD_N + 0.3
flash_io3 Flash SPI channel 0 signal inout -0.5 xAVDD_N + 0.3
gpio_15 GPIO channel 15 signal output -0.5 VDD3V3 + 0.3
gpio_14 GPIO channel 14 signal output -0.5 VDD3V3 + 0.3
gpio_13 GPIO channel 13 signal output -0.5 VDD3V3 + 0.3
gpio_12 GPIO channel 12 signal output -0.5 VDD3V3 + 0.3
gpio_11 GPIO channel 11 signal output -0.5 VDD3V3 + 0.3
gpio_10 GPIO channel 10 signal output -0.5 VDD3V3 + 0.3
gpio_9 GPIO channel 9 signal output -0.5 VDD3V3 + 0.3
gpio_8 GPIO channel 8 signal output -0.5 VDD3V3 + 0.3
gpio_7 GPIO channel 7 signal output -0.5 VDD3V3 + 0.3
gpio_6 GPIO channel 6 signal output -0.5 VDD3V3 + 0.3
gpio_5 GPIO channel 5 signal output -0.5 VDD3V3 + 0.3
gpio_4 GPIO channel 4 signal output -0.5 VDD3V3 + 0.3
gpio_3 GPIO channel 3 signal output -0.5 VDD3V3 + 0.3
gpio_2 GPIO channel 2 signal output -0.5 VDD3V3 + 0.3
gpio_1 GPIO channel 1 signal output -0.5 VDD3V3 + 0.3
gpio_0 GPIO channel 0 signal output -0.5 VDD3V3 + 0.3
adc_high ADC and DAC reference voltage (high) analog input -0.5 VDD3V3 + 0.5
adc_low ADC and DAC reference voltage (low) analog input -0.5 VDD3V3 + 0.5
adc0_in ADC0 analog input analog input -0.5 VDD3V3 + 0.5
adc1_in ADC1 analog input analog input -0.5 VDD3V3 + 0.5
comp_inn Comparator negative input analog input -0.5 VDD3V3 + 0.5
comp_inp Comparator positive input analog input -0.5 VDD3V3 + 0.5
analog_out DAC and bandgap analog output analog output 0.0 VDD3V3
VDD1V8 Core Analog/Digital voltage (output) power inout 1.5 2.1
VDD3V3 Common Analog/Digital power supply power inout 3.6 3.0
GND Common Analog/Digital Ground ground inout 0 0

Global Conditions

Name Typical Minimum Maximum Units
VDD3V3 3.3 V
Ground 0 V
Corner tm
Sigma 3

Electrical Parameters

Parameter Pin Typical Minimum Maximum Units Conditions

Physical Parameters

Parameter Typical Minimum Maximum Units
device_area µm²
area µm²
width µm
height µm
DRC_errors
LVS_errors

Figure(s)

raven_pic_annotated.png

Figure 1

raven_symbol.svg

Figure 2

raven_block_diagram.png

Figure 3

Performance Characteristics

Summary

Catalog ID

RAVEN_CSP

IP Provider

N/A

Designer

R. Timothy Edwards

Type

Hard IP

Node

180nm

Vendor

efabless

Foundry

N/A

Process

EFXH018D

Category

N/A

Certifications

Licensing

Info

Contact Designer

Maturity

Stage

layout

# of Tries

0

Library Package

Version

9.0

Version Date

Aug 13, 2019

Dependencies

AMUX2_3V

AMUX4_3V

LS_3VX2

XSPRAMBLP_1024X32_M8P