Raptor is a full SoC reference design for IoT applications based on the Arm Cortex M0 or M3 CPU core targeted on the X-FAB XH018 process (180nm).  Raptor provides means to interface with analog and digital sensors as well as external RF radio (WIFI, Cellular, Bluetooth, etc.,) modules needed for IoT applications.

The reference design is based on an SoC design template and can be modified, compiled and simulated through the SoC Editor tool with CloudV on the Efabless platform. The reference design comes with basic device drivers for all on-chip peripherals as well as set of applications to test and demonstrate Raptor capabilities.

Instances of the Raptor Design Template can be configured through the Design Request Form.   A configuration file is generated upon saving the form and can be used as a starting point for generating a reference design or to request a turn-key delivery of a custom SoC through design partners on the Efabless platform.

Below is the block diagram for a Demo Chip configuration taped-out for Raptor.  The design files for project include an instance of Raptor based on the configuration shown below.

Block Diagram for Demo Chip Configuration

Raptor can be clocked using external or internal clock sources. Raptor has 10MHz internal RC oscillator as well as the necessary circuitry to attach external crystal oscillator (1-4 MHz). In addition to that, Raptor employs a PLL and clock dividers to enable the system to run at clock frequency that ranges from 500KHz up to 80 MHz under software control. The following diagram shows Raptor clocking subsystem.

Clock Tree

Demo Chip Layout