Efabless Logo

ARM CortexM0 processor with digital, analog, and mixed-signal peripherals, and 16kB on-board SRAM

  • ARM CortexM0
  • 16kB on-board SRAM
  • 2 10-bit ADCs
  • 1 10-bit DAC
  • 80 MHz on-board oscillator
  • analog comparator
  • bandgap voltage reference

Pins

Name Description Type Direction Vmin Vmax
AHB_GPIOEN0 TBD digital output -0.5 VDD + 0.3
AHB_GPIOIN0 TBD digital input -0.5 VDD + 0.3
AHB_GPIOOUT0 TBD digital output -0.5 VDD + 0.3
AHB_GPIOPD0 TBD digital output -0.5 VDD + 0.3
AHB_GPIOPU0 TBD digital output -0.5 VDD + 0.3
AHB_MSI_0 TBD signal input -0.5 VDD + 0.3
AHB_MSO_0 TBD signal output -0.5 VDD + 0.3
AHB_SCLK_0 TBD signal output -0.5 VDD + 0.3
AHB_SSn_0 TBD signal output -0.5 VDD + 0.3
APB_MSI_0 TBD signal input -0.5 VDD + 0.3
APB_MSO_0 TBD signal output -0.5 VDD + 0.3
APB_SCLK_0 TBD signal output -0.5 VDD + 0.3
APB_SSn_0 TBD signal output -0.5 VDD + 0.3
DBGIO0 TBD digital output -0.5 VDD + 0.3
HADDR TBD digital input -0.5 VDD + 0.3
HBURST TBD digital input -0.5 VDD + 0.3
HCLK TBD signal output -0.5 VDD + 0.3
HMASTLOCK TBD signal input -0.5 VDD + 0.3
HPROT TBD digital input -0.5 VDD + 0.3
HRDATA TBD digital output -0.5 VDD + 0.3
HREADY TBD signal output -0.5 VDD + 0.3
HRESETn TBD signal input -0.5 VDD + 0.3
HRESP TBD signal output -0.5 VDD + 0.3
HSIZE TBD digital input -0.5 VDD + 0.3
HTRANS TBD digital input -0.5 VDD + 0.3
HWDATA TBD digital input -0.5 VDD + 0.3
HWRITE TBD signal input -0.5 VDD + 0.3
IRQ TBD digital output -0.5 VDD + 0.3
LOCKUP TBD signal input -0.5 VDD + 0.3
PWMO_0 TBD signal output -0.5 VDD + 0.3
PWMO_1 TBD signal output -0.5 VDD + 0.3
RESETn TBD signal input -0.5 VDD + 0.3
RsRx_0 TBD signal input -0.5 VDD + 0.3
RsRx_1 TBD signal input -0.5 VDD + 0.3
RsTx_0 TBD signal output -0.5 VDD + 0.3
RsTx_1 TBD signal output -0.5 VDD + 0.3
SRAMADDR TBD digital output -0.5 VDD + 0.3
SRAMCS TBD signal output -0.5 VDD + 0.3
SRAMRDATA TBD digital input -0.5 VDD + 0.3
SRAMWDATA TBD digital output -0.5 VDD + 0.3
SRAMWEN TBD digital output -0.5 VDD + 0.3
TOUT0 TBD signal output -0.5 VDD + 0.3
adc_clk_0 TBD signal output -0.5 VDD + 0.3
adc_clk_1 TBD signal output -0.5 VDD + 0.3
adc_data_0 TBD digital input -0.5 VDD + 0.3
adc_data_1 TBD digital input -0.5 VDD + 0.3
adc_en_0 TBD signal output -0.5 VDD + 0.3
adc_en_1 TBD signal output -0.5 VDD + 0.3
adc_eoc_0 TBD signal input -0.5 VDD + 0.3
adc_eoc_1 TBD signal input -0.5 VDD + 0.3
adc_mux_sel_0 TBD digital output -0.5 VDD + 0.3
adc_mux_sel_1 TBD digital output -0.5 VDD + 0.3
adc_start_0 TBD signal output -0.5 VDD + 0.3
adc_start_1 TBD signal output -0.5 VDD + 0.3
adc_vrefh_sel_0 TBD signal output -0.5 VDD + 0.3
adc_vrefh_sel_1 TBD signal output -0.5 VDD + 0.3
bg_en_0 TBD signal output -0.5 VDD + 0.3
clk_hse TBD signal input -0.5 VDD + 0.3
clk_hsi TBD signal input -0.5 VDD + 0.3
clk_pll_in TBD signal input -0.5 VDD + 0.3
clk_pll_out TBD signal output -0.5 VDD + 0.3
comp_ena_0 TBD signal output -0.5 VDD + 0.3
comp_ninputsrc_0 TBD digital output -0.5 VDD + 0.3
comp_out_0 TBD signal input -0.5 VDD + 0.3
comp_pinputsrc_0 TBD digital output -0.5 VDD + 0.3
dac_data_0 TBD digital output -0.5 VDD + 0.3
dac_en_0 TBD signal output -0.5 VDD + 0.3
dac_vrefh_sel_0 TBD signal output -0.5 VDD + 0.3
fcen TBD signal output -0.5 VDD + 0.3
fdi TBD digital input -0.5 VDD + 0.3
fdo TBD digital output -0.5 VDD + 0.3
fdoe TBD digital output -0.5 VDD + 0.3
fsclk TBD signal output -0.5 VDD + 0.3
hse_ena TBD signal output -0.5 VDD + 0.3
hsi_ena TBD signal output -0.5 VDD + 0.3
pll_cp_ena_lv TBD signal output -0.5 VDD + 0.3
pll_trim TBD signal output -0.5 VDD + 0.3
pll_vco_ena_lv TBD signal output -0.5 VDD + 0.3
rst_lv TBD signal input -0.5 VDD + 0.3
scl_i_0 TBD signal input -0.5 VDD + 0.3
scl_o_0 TBD signal output -0.5 VDD + 0.3
scl_oen_o_0 TBD signal output -0.5 VDD + 0.3
sda_i_0 TBD signal input -0.5 VDD + 0.3
sda_o_0 TBD signal output -0.5 VDD + 0.3
sda_oen_o_0 TBD signal output -0.5 VDD + 0.3
spi_clk_0 TBD signal output -0.5 VDD + 0.3
spi_cs_0 TBD signal output -0.5 VDD + 0.3
spi_io_0 TBD digital inout -0.5 VDD + 0.3

Physical Parameters

Parameter Typical Minimum Maximum Units
device_area µm²
area µm²
width µm
DRC_errors
LVS_errors

Figure(s)

raptor_demo_symbol.svg

Figure 1

Performance Characteristics

Summary

Catalog ID

RAPTOR_DEMO

IP Provider

N/A

Designer

eFabless engineering

Type

N/A

Node

180nm

Vendor

efabless

Foundry

N/A

Process

EFXH018D

Category

Processor

Certifications

Licensing

Info

Contact Designer

Maturity

Stage

layout

# of Tries

2

Library Package

Version

1

Version Date

Sep 19, 2019